1. Field of the Invention
The present invention relates to a data slicer circuit.
2. Description of the Related Art
The teletext system used in Europe is among systems for superimposing data indicative of characters and others on a video signal to be received by a television receiver. Teletext is a technique of superimposing and transmitting data indicative of characters and others during vertical blanking intervals of the video signal. To observe characters and others on the television receiver, a circuit is required to separate data from the incoming video signal, and the data slicer circuit serves the function of separating this superimposed data from the video signal. Teletext has a clock-run-in signal (“pulse signal”) indicating the presence/absence of data, and the data slicer circuit separates data from the video signal by setting the midpoint of the amplitude of the clock-run-in signal defined in advance as a slice level and using the slice level as a reference.
If, however, the video signal undergoes a tuning deviation or a change in receiving condition due to the TV receiver, the clock-run-in signal may change its waveform. This makes it impossible for the data slicer circuit to accurately separate data as the slice level is no longer at the midpoint of the amplitude of the clock-run-in signal as a result of distortion of the waveform of the clock-run-in signal or variations in amplitude thereof. For this reason, a data slicer circuit is suggested that is capable of accurately determining a slice level and reading out data even in the event of a change in waveform of the clock-run-in signal (see, e.g., Japanese Patent Application Laid-Open Publication No. Hei. 11-41552).
FIG. 6 is a block diagram showing a conventional data slicer circuit.
The conventional data slicer circuit has a peak hold circuit 90 for holding the upper peak voltage of the clock-run-in signal, a peak hold circuit 91 for holding the lower peak voltage of the clock-run-in signal, resistors R1 and R2 equal in resistance and a comparator 41. And, the peak hold circuits 90 and 91 each have a comparator, an op-amp, a resistor and a capacitor that are not shown.
A video signal is supplied not only to the positive (non-inverting input) terminal of the comparator 41 but also to the peak hold circuits 90 and 91. The difference of the upper peak value detected by the peak hold circuit 90 and the lower peak value detected by the peak hold circuit 91 are voltage-divided between the resistors R1 (approx. 10 KΩ) and R2 (approx. 10 KΩ). The intermediate voltage produced by dividing the voltage between the resistors R1 and R2 is supplied to the negative (inverting input) terminal of the comparator 41 as a slice level for extracting binary data consisting of logic values 1's and 0's from the data representing characters and other information. Then, the video signal and the slice level are compared by the comparator 40, outputting the comparison result as “HIGH (logic 1)” or “LOW (logic 0).”
FIG. 7 is a waveform diagram showing the operation of the conventional data slice circuit. The upper peak value of the clock-run-in signal is detected by the peak hold circuit 90, whereas the lower peak value of the clock-run-in signal is detected by the peak hold circuit 91. The slice level is determined by calculating the midpoint between the upper and lower peak values. This makes it possible to retain the slice level at the midpoint level of the amplitude of the clock-run-in signal even in the event of a distortion or change in the amplitude of the clock-run-in signal.
In such a conventional data slicer circuit, two peak hold circuits are required to detect the upper and lower peak values of the clock-run-in signal. Each of the peak hold circuits contains an op-amp, a capacitor and a resistor that are large in area, resulting in a large circuit and giving rise to a problem of large chip size when integrated into a chip. Besides, the conventional data slicer circuit has the problem of increased manufacturing cost.